Datasheet

Datasheet 63

3 Register Description

3.1 Conceptual Overview of the Platform Configuration

Structure

The Intel 852GME GMCH, Intel 852PM MCH and ICH4-M are physically connected by hub

interface. From a configuration standpoint, the hub interface is logically PCI bus #0. As a result,

all devices internal to the GMCH/MCH and ICH4-M appear to be on PCI bus #0. The system’s

primary PCI expansion bus is physically attached to the ICH4-M and from a configuration

perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge and therefore has a

programmable PCI Bus number. Note that the primary PCI bus is referred to as PCI_A in this

document and is not PCI bus #0 from a configuration standpoint. The AGP appears to system

software to be real PCI bus behind PCI-to-PCI bridges resident as devices on PCI bus #0.

The GMCH/MCH contains two PCI devices within a single physical component. The

configuration registers for the three devices are mapped as devices residing on PCI bus #0.

Device #0: Host-Hub Interface Bridge/DDR SDRAM Controller. Logically this appears as a PCI

device residing on PCI bus #0. Physically, Device #0 contains the standard PCI registers, DDR

SDRAM registers, the Graphics Aperture Controller registers, Hub Interface Control registers and

other GMCH/MCH specific registers. Device #0 is divided into the following functions:

Function #0

: Host Bridge Legacy registers including Graphics Aperture Control registers, Hub

Interface Configuration registers and Interrupt Control registers

Function #1

: DDR SDRAM Interface Registers

Function #3

: Intel Configuration Process Registers

Device #1: Host-AGP Bridge. Logically this appears as a “virtual” PCI-to-PCI bridge residing on

PCI bus #0. Physically Device #1 contains the standard PCI-to-PCI bridge registers and the

standard AGP/PCI configuration registers (including the AGP I/O and memory address mapping).

Device #2: Integrated Graphics Controller. Logically this appears as a PCI device residing on PCI

bus #0. Physically Device #2 contains the Configuration registers for 2D, 3D, and display

functions. Table 27 shows the Device # assignment for the various internal GMCH/MCH devices.