Datasheet

R
6 Datasheet
3.10.19
PMLIMIT1 - Prefetchable Memory Limit Address Reg (Device #1) ...146
3.10.20 BCTRL - Bridge Control Register (Device #1).................................... 147
3.10.21 ERRCMD1 - Error Command Register (Device #1)...........................148
3.11 Intel
®
852GME GMCH Integrated Graphics Device Registers (Device #2,
Function #0)........................................................................................................149
3.11.1 VID – Vendor Identification Register (Device #2)...............................150
3.11.2 DID – Device Identification Register (Device #2) ............................... 150
3.11.3 PCICMD – PCI Command Register (Device #2)................................151
3.11.4 PCISTS – PCI Status Register (Device #2)........................................ 152
3.11.5 RID – Revision Identification Register (Device #2) ............................152
3.11.6 CC – Class Code Register (Device #2)..............................................153
3.11.7 CLS – Cache Line Size Register (Device #2) .................................... 153
3.11.8 MLT – Master Latency Timer Register (Device #2)............................153
3.11.9 HDR – Header Type Register (Device #2) .........................................154
3.11.10 GMADR – Graphics Memory Range Address Register (Device #2)..154
3.11.11 MMADR – Memory Mapped Range Address Register (Device #2)...155
3.11.12 IOBAR – I/O Base Address Register (Device #2) .............................. 155
3.11.13 SVID – Subsystem Vendor Identification Register (Device #2)..........156
3.11.14 SID – Subsystem Identification Register (Device #2).........................156
3.11.15 ROMADR – Video BIOS ROM Base Address Registers (Device #2) 156
3.11.16 INTRLINE⎯Interrupt Line Register (Device #2) ................................157
3.11.17 INTRPIN⎯Interrupt Pin Register (Device #2) ....................................157
3.11.18 MINGNT – Minimum Grant Register (Device #2)...............................157
3.11.19 MAXLAT – Maximum Latency Register (Device #2) ..........................158
3.11.20 PMCAP – Power Management Capabilities Register (Device #2)..... 158
3.11.21 PMCS – Power Management Control/Status Register (Device #2)...159
3.11.22 GCCC ⎯ GMCH Clock Control Register ...........................................160
4 System Address Map......................................................................................................161
4.1 System Memory Address Ranges...................................................................... 161
4.2 MS-DOS* Compatibility Area ............................................................................. 163
4.3 Extended System Memory Area......................................................................... 165
4.4 Main System Memory Address Range (0010_0000h to Top of Main Memory). 166
4.4.1 15 MB – 16 MB Window .....................................................................166
4.4.2 Pre-allocated System Memory............................................................166
4.4.3 System Management Mode (SMM) Memory Range ..........................170
4.4.4 System Memory Shadowing............................................................... 172
4.4.5 I/O Address Space..............................................................................172
4.4.6 GMCH Decode Rules and Cross-Bridge Address Mapping...............173
5 Functional Description ....................................................................................................177
5.1 Host Interface Overview .....................................................................................177
5.2 Dynamic Bus Inversion.......................................................................................177
5.2.1 System Bus Interrupt Delivery ............................................................177
5.2.2 Upstream Interrupt Messages ............................................................178
5.3 System Memory Interface ..................................................................................178
5.3.1 DDR SDRAM Interface Overview.......................................................178
5.3.2 Memory Organization and Configuration............................................179
5.3.3 DDR SDRAM Performance Description .............................................180
5.3.4 Intel
®
852GME GMCH and Intel
®
852PM MCH Data Integrity (ECC) 180
5.4 Integrated Graphics Overview............................................................................180
5.4.1 Intel
®
GMCH 3D/2D Instruction Processing .......................................181