Datasheet

Signal Description
R
Datasheet 53
2.9.1 Full and Warm Reset State
Figure 3 . Full and Warm Reset Waveforms
1 ms min
ICH4-M Power
ICH4-M PWROK In
ICH4-M PCIRST# Out
GMCH/MCH RSTIN# In
GMCH/MCH Power
GMCH/MCH PWROK In
Full Reset
1 ms min
Unknown
Warm
Reset
Running Warm Reset Running
GMCH/MCH Reset State
write to CF9h
GMCH/MCH CPURST# Out
1 ms 1 ms
All register bits assume their default values during full reset. PCIRST# resets all internal flops and
state machines (except for a few configuration register bits). A full reset occurs when PCIRST#
(RSTIN#) and CPURST# are asserted and PWROK is deasserted. This means that all the registers
are changed to their default values in the entire system. A warm reset (CPU only reset) occurs
when PCIRST# (RSTIN#) is asserted and PWROK is asserted. CPU only reset drives only
CPURST# and can be initiated by write of a bit in dedicated register and HALT special cycle. As
a result, CPU only registers must be reset. Table 20 describes the reset states.
The PWROK input pin is used to latch the GMCH/MCH strap values upon exiting S3. This
imposes a system requirement in that the ICH4-M expects power to be removed (PWROK to go
low) when SLP_S3# goes low.
Table 20. Full and Warm Reset Waveforms
Reset State RSTIN# PWROK
Full Reset L L
Warm Reset L H
Doesn’t Occur H L
Normal Operation H H