Datasheet

Signal Description
R
46 Datasheet
2.6.4 GMCH DVO & I
2
C to AGP Pin Mapping
The GMCH will mux a DVODETECT signal with the GPAR signal on the AGP bus. This signal
will act as a strap and indicate whether the interface is in AGP or DVO mode. The GMCH/MCH
has an internal pull-down on DVODETECT signal that will by default pull it low. For an AGP
graphics device, pin should be pulled up high and the AGP/DVO Mux select bit in the SHIC
(Device 0, function 0, offset 74h bit 1) register will be set to AGP mode (AGP/DVO Mux Strap =
1). Boards that use only Integrated Graphics should leave DVODETECT NC (No Connect). If
board has digital display devices connected to the AGP/DVO interface, SBA [7:0] will act as
straps for an ADDID.
Table 16. Intel
®
852GME GMCH AGP/DVO Pin Muxing
DVO MODE AGP MODE DVO MODE AGP MODE DVO MODE AGP MODE
DVOBD[0] GAD[3] DVOCD[0] GAD[19] MI2CCLK GIRDY#
DVOBD[1] GAD[2] DVOCD[1] GAD[20] MI2CDATA GDEVSEL#
DVOBD[2] GAD[5] DVOCD[2] GAD[21] MDVICLK GTRDY#
DVOBD[3] GAD[4] DVOCD[3] GAD[22] MDVIDATA GFRAME#
DVOBD[4] GAD[7] DVOCD[4] GAD[23] MDDCCDATA GAD[15]
DVOBD[5] GAD[6] DVOCD[5] GCBE#[3] MDDCCLK GSTOP#
DVOBD[6] GAD[8] DVOCD[6] GAD[25] DVOBCINT# GAD[30]
DVOBD[7] GCBE#[0] DVOCD[7] GAD[24] DVOBCCLKINT GAD[13]
DVOBD[8] GAD[10] DVOCD[8] GAD[27] ADDID[7] GSBA[7]
DVOBD[9] GAD[9] DVOCD[9] GAD[26] ADDID[6] GSBA[6]
DVOBD[10] GAD[12] DVOCD[10] GAD[29] ADDID[5] GSBA[5]
DVOBD[11] GAD[11] DVOCD[11] GAD[28] ADDID[4] GSBA[4]
DVOBCLK GADSTB[0] DVOCCLK GADSTB[1] ADDID[3] GSBA[3]
DVOBCLK# GADSTB#[0] DVOCCLK# GADSTB#[1] ADDID[2] GSBA[2]
DVOBHSYNC GAD[0] DVOCHSYNC GAD[17] ADDID[1] GSBA[1]
DVOBVSYNC GAD[1] DVOCVSYNC GAD[16] ADDID[0] GSBA[0]
DVOBBLANK# GCBE#[1] DVOCBLANK# GAD[18] DVODETECT GPAR
DVOBFLDSTL GAD[14] DVOCFLDSTL GAD[31] DPMS GPIPE#