Datasheet

Signal Description
R
Datasheet 41
Signal Name Type Description
DVOBCCLKINT I
DVO
DVOBC Pixel Clock Input/Interrupt:
This input can be programmed to be either a TV reference clock input from
a TV encoder or an Interrupt input pin for LFP display Hot Plug support.
DVOBC Pixel Clock Input: This signal may be configured as the reference
clock input from a TV-OUT device. The maximum input frequency for this
signal is 85 MHz.
DVOBC Interrupt: This signal may be configured as an interrupt input for
Hot plug support.
DVOBCCLKINT needs to be pulled down if the signal is NOT used.
DPMS I
DVO
Display Power Management Signaling: This signal is used only in mobile
systems to act as the DREFCLK in certain power management states (i.e.
Display Power Down Mode); DPMS Clock is used to refresh video during
S1-M. Clock Chip is powered down in S1-M. DPMS should come from a
clock source that runs during S1-M and needs to be 1.5 V. So, an example
would be to use a 1.5 V version of SUSCLK from ICH4-M.
DAC Clocking
DREFCLK I
LVTTL
Display Clock Input: This pin is used to provide a 48 MHz input clock to
the Display PLL that is used for 2D/Video and DAC.
LVDS LCD Flat Panel Clocking
DREFSSCLK
I
LVTTL
Display SSC Clock Input: This pin provides a 48 MHz or 66 MHz input
clock (SSC or non-SSC) to the Display PLL B.