Datasheet

Signal Description
R
40 Datasheet
2.5 Clocks
Table 11. Clock Signals
Signal Name Type Description
Host Processor Clocking
BCLK
BCLK#
I
CMOS
Differential Host Clock In: These pins receive a buffered host clock from
the external clock synthesizer. This clock is used by all of the GMCH/MCH
logic that is in the Host clock domain (host, hub and system memory). The
clock is also the reference clock for the graphics core PLL. This is a low
voltage differential input.
System Memory Clocking
SCK[5:0] O
SSTL_2
Differential DDR SDRAM Clock: SCK and SCK# pairs are differential
clock outputs. The crossing of the positive edge of SCK and the negative
edge of SCK# is used to sample the address and control signals on the
DDR SDRAM. There are 3 pairs to each SO-DIMM.
NOTE: Intel 852GME ECC error detection is supported by the SCK[2] and
SCK[5] signals.
SCK[5:0]# O
SSTL_2
Complementary Differential DDR SDRAM Clock: These are the
complimentary differential DDR SDRAM clock signals.
NOTE: Intel 852GME/852PM: ECC error detection is supported by the
SCK[2]# and SCK[5]# signals.
DVO/Hub Input Clocking
GCLKIN I
CMOS
Input Clock: 66 MHz, 3.3 V input clock from external buffer DVO/hub
interface.
DVO Clocking
DVOBCLK
DVOBCLK#
O
DVO
Differential DVO Clock Output: These pins provide a differential pair
reference clock that can run up to 165 MHz.
DVOBCLK corresponds to the primary clock out.
DVOBCLK# corresponds to the primary complementary clock out.
DVOCCLK
DVOCCLK#
O
DVO
Differential DVO Clock Output: These pins provide a differential pair
reference clock that can run up to 165 MHz.
DVOCCLK corresponds to the primary clock out.
DVOCCLK# corresponds to the primary complementary clock out.