Datasheet

R
4 Datasheet
3
Register Description..........................................................................................................63
3.1 Conceptual Overview of the Platform Configuration Structure ............................63
3.2 Nomenclature for Access Attributes.....................................................................64
3.3 Standard PCI Bus Configuration Mechanism.......................................................65
3.4 Routing Configuration Accesses .......................................................................... 65
3.4.1 PCI Bus #0 Configuration Mechanism..................................................65
3.4.2 Primary PCI and Downstream Configuration Mechanism....................66
3.4.3 AGP/PCI_B Bus Configuration Mechanism.......................................... 66
3.5 Register Definitions ..............................................................................................67
3.6 I/O Mapped Registers ..........................................................................................68
3.6.1 CONFIG_ADDRESS – Configuration Address Register...................... 68
3.6.2 CONFIG_DATA – Configuration Data Register ...................................70
3.7 Host-Hub Interface Bridge Device Registers (Device #0, Function #0)...............71
3.7.1 VID – Vendor Identification Register (Device #0).................................73
3.7.2 DID – Device Identification Register (Device #0) ................................. 73
3.7.3 PCICMD – PCI Command Register (Device #0)..................................74
3.7.4 PCI Status Register (Device #0)...........................................................75
3.7.5 RID – Revision Identification (Device #0)............................................. 76
3.7.6 SUBC – Sub Class Code Register (Device #0).................................... 76
3.7.7 BCC – Base Class Code Register (Device #0) .................................... 77
3.7.8 HDR – Header Type Register (Device #0) ........................................... 77
3.7.9 APBASE – Aperture Base Configuration (Device #0) ..........................78
3.7.10 SVID – Subsystem Vendor Identification Register (Device #0)............79
3.7.11 SID – Subsystem Identification Register (Device #0)........................... 79
3.7.12 CAPPTR – Capabilities Pointer Register (Device #0).......................... 79
3.7.13 CAPID⎯Capability Identification Register (Device #0)........................80
3.7.14 RRBAR – Register Range Base Address Register (Device #0) ..........81
3.7.15 GMC – GMCH Miscellaneous Control Register (Device #0)................ 82
3.7.16 GGC – GMCH Graphics Control Register (Device 0) .......................... 83
3.7.17 DAFC – Device and Function Control Register (Device 0) ..................84
3.7.18 FDHC – Fixed DRAM Hole Control Register (Device #0) .................... 85
3.7.19 PAM(6:0) – Programmable Attribute Map Register (Device #0) ..........85
3.7.20 SMRAM – System Management RAM Control Register (Device #0) ..90
3.7.21 ESMRAMC – Extended System Management RAM Control
(Device #0)............................................................................................ 91
3.7.22 ERRSTS – Error Status Register (Device #0)...................................... 92
3.7.23 ERRCMD – Error Command Register (Device #0) ..............................93
3.7.24 SMICMD – SMI Error Command Register (Device #0)........................94
3.7.25 SCICMD – SCI Error Command Register (Device #0)......................... 95
3.7.26 SHIC - Secondary Host Interface Control Register (Device #0) ..........96
3.7.27 ACAPID – AGP Capability Identifier Register (Device #0)................... 96
3.7.28 AGPSTAT – AGP Status Register (Device #0) ....................................97
3.7.29 AGPCMD – AGP Command Register (Device #0)............................... 98
3.7.30 AGPCTRL – AGP Control Register (Device #0) .................................. 99
3.7.31 AFT – AGP Functional Register (Device #0)........................................99
3.7.32 APSIZE – Aperture Size (Device #0)..................................................100
3.7.33 ATTBASE – Aperture Translation Table Base Register (Device #0) .101
3.7.34 AMTT – AGP Interface Multi-Transaction Timer Register
(Device #0).......................................................................................... 102
3.7.35 LPTT – Low Priority Transaction Timer Register (Device #0)............103
3.8 Main Memory Control, Memory I/O Control Registers (Device #0, Function #1)104