Datasheet

R
Datasheet 3
Contents
1
Overview ...........................................................................................................................17
1.1 Terminology..........................................................................................................17
1.2 Reference Documents.......................................................................................... 19
1.3 System Architecture Overview .............................................................................20
1.3.1 Intel
®
852GME GMCH System Architecture.........................................20
1.3.2 Intel
®
852PM MCH System Architecture ..............................................20
1.4 Processor Host Interface...................................................................................... 21
1.4.1 Host Bus Error Checking ......................................................................21
1.5 Intel
®
852PM and 852GME DDR SDRAM Interface ............................................ 21
1.6 GMCH Internal Graphics Interface....................................................................... 22
1.6.1 GMCH Analog Display Port ..................................................................23
1.6.2 GMCH Integrated LVDS Port................................................................23
1.6.3 GMCH Integrated DVO Port .................................................................23
1.7 External AGP Graphics Interface .........................................................................23
1.7.1 Intel
®
852PM MCH and Intel
®
852GME GMCH AGP Interface............23
1.8 Hub Interface........................................................................................................24
1.9 Address Decode Policies ..................................................................................... 24
1.10 Platform Clocking ................................................................................................. 24
1.11 System Interrupts ................................................................................................. 25
2 Signal Description ............................................................................................................. 27
2.1 Host Interface Signals .......................................................................................... 28
2.2 DDR SDRAM Interface.........................................................................................31
2.3 AGP Interface Signals ..........................................................................................33
2.3.1 AGP Addressing Signals ...................................................................... 33
2.3.2 AGP Flow Control Signals ....................................................................34
2.3.3 AGP Status Signals ..............................................................................35
2.3.4 AGP Strobes......................................................................................... 36
2.3.5 AGP/PCI Signals-Semantics ................................................................37
2.4 Hub Interface Signals...........................................................................................39
2.5 Clocks...................................................................................................................40
2.6 GMCH Internal Graphics Display Signals ............................................................ 42
2.6.1 Dedicated LVDS Panel Interface..........................................................42
2.6.2 Digital Video Port B (DVOB)................................................................. 43
2.6.3 Digital Video Port C (DVOC)................................................................. 44
2.6.4 GMCH DVO & I
2
C to AGP Pin Mapping............................................... 46
2.6.5 Analog Display......................................................................................47
2.6.6 Graphics General Purpose Input/Output Signals ................................. 48
2.7 Power Sequencing Signal Description................................................................. 49
2.8 Voltage References, PLL Power ..........................................................................50
2.9 Reset States and Pull-up/Pull-downs...................................................................52
2.9.1 Full and Warm Reset State...................................................................53