Datasheet

Signal Description
R
Datasheet 29
Signal Name Type Description
DPSLP# I
CMOS
Deep Sleep #: This signal comes from the ICH4-M device, providing an
indication of C3 and C4 state control to the CPU. Deassertion of this
signal is used as an early indication for C3 and C4 wake up (to active
HPLL).
Note that this is a low Voltage CMOS buffer operating on the FSB VTT
power plane.
DRDY# I/O
AGTL+
Data Ready: Asserted for each cycle that data is transferred.
HA[31:3]# I/O
AGTL+
Host Address Bus: HA[31:3]# connects to the CPU address bus. During
processor cycles the HA[31:3]# are inputs. The GMCH/MCH drive
HA[31:3]# during snoop cycles on behalf of hub interface. HA[31:3]# are
transferred at 2X rate. Note that the address is inverted on the CPU bus.
HADSTB[1:0]# I/O
AGTL+
Host Address Strobe: HA[31:3]# connects to the CPU address bus.
During CPU cycles, the source synchronous strobes are used to transfer
HA[31:3]# and HREQ[4:0]# at the 2X transfer rate.
Strobe
Address Bits
HADSTB[0]# HA[16:3]#, HREQ[4:0]#
HADSTB[1]# HA[31:17]#
HD[63:0]# I/O
AGTL+
Host Data: These signals are connected to the CPU data bus. HD[63:0]#
are transferred at 4X rate. Note that the data signals are inverted on the
CPU bus.
HDSTBP[3:0]#
HDSTBN[3:0]#
I/O
AGTL+
Differential Host Data Strobes: The differential source synchronous
strobes are used to transfer HD[63:0]# and DINV[3:0]# at the 4X transfer
rate.
Strobe
Data Bits
HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, DINV[3]#
HDSTBP[2]#, HDSTBN[2]# HD[47:32]#, DINV[2]#
HDSTBP[1]#, HDSTBN[1]# HD[31:16]#, DINV[1]#
HDSTBP[0]#, HDSTBN[0]# HD[15:0]#, DINV[0]#
HIT# I/O
AGTL+
Hit: Indicates that a caching agent holds an unmodified version of the
requested line. Also, driven in conjunction with HITM# by the target to
extend the snoop window.
HITM# I/O
AGTL+
Hit Modified: Indicates that a caching agent holds a modified version of
the requested line and that this agent assumes responsibility for providing
the line. Also, driven in conjunction with HIT# to extend the snoop window.
HLOCK# I/O
AGTL+
Host Lock: All CPU bus cycles sampled with the assertion of HLOCK#
and ADS#, until the negation of HLOCK# must be atomic, i.e. no hub
interface snoopable access to system memory is allowed when HLOCK#
is asserted by the CPU.