Datasheet

Signal Description

Datasheet 27

2 Signal Description

This section describes the GMCH/MCH signals. These signals are arranged in functional groups

according to their associated interface. The following notations are used to describe the signal

type:

I Input pin

O Output pin

I/O Bi-directional Input/Output pin

The signal description also includes the type of buffer used for the particular signal:

AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for

complete details. The GMCH integrates AGTL+ termination resistors, and

AGTL+ signals are “inverted bus” style where a low voltage represents a

logical 1.

DVO DVO buffers (1.5 V tolerant)

AGP AGP interface signals. These signals are compatible with AGP 2.0 1.5 V

Signaling Environment DC and AC Specifications. The buffers are 1.5 V

tolerant

Hub Compatible to hub interface 1.5

SSTL_2 Stub series termination logic compatible signals (2.5 V tolerant)

LVTTL Low voltage TTL compatible signals (3.3 V tolerant)

CMOS CMOS buffers (3.3 V tolerant)

LVDS Low voltage differential signal interface

Analog Analog signal interface

Ref Voltage reference signal

System Address and Data Bus signals are logically inverted signals. In other words, the actual

values are inverted of what appears on the system bus. This must be taken into account and the

addresses and data bus signals must be inverted inside the GMCH/MCH. All processor control

signals follow normal convention: A 0 indicates an active level (low voltage), and a 1 indicates an

active level (high voltage).