Datasheet
Overview
R
Datasheet 25
AGP and hub interface run at a constant 66 MHz base frequency. The hub interface runs at 4X,
while AGP transfers may be at 1X, 2X, or 4X.
The following table indicates the frequency ratios between the various interfaces that the
GMCH/MCH supports:
Table 2. Intel
®
852GME GMCH Interface Clocks
Interface Clock
Speed
CPU System
Bus
Frequency
Ratio
Sample
s Per
Clock
Data Rate
(Mega-
samples/s)
Data
Width
(Bytes)
Peak
Bandwidth
(MB/s)
CPU Bus 133 MHz Reference 4 533 8 4264
DDR
SDRAM
133 MHz 1:1
Synchronous
2 266 8 2128
166 MHz 1:1
Synchronous
2 333 8 2664
AGP 66 MHz Asynchronous AGP
Spec
AGP Spec AGP Spec AGP Spec
1.11 System Interrupts
The GMCH/MCH supports both the legacy Intel 8259 Programmable Interrupt delivery
mechanism and the respective processor Interrupt delivery mechanism. The serial APIC Interrupt
mechanism is not supported.
The Intel 8259 Interrupt delivery mechanism support consists of flushing in bound hub interface
write buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the hub
interface.
PCI MSI interrupts are generated as Memory Writes. The GMCH/MCH decodes upstream
Memory Writes to the range 0FEE0_0000h - 0FEEF_FFFFh from the AGP and hub interface as
message-based interrupts. The GMCH/MCH forwards the Memory Writes along with the
associated write data to the system bus as an Interrupt Message transaction. Since this address
does not decode as part of main system memory, the write cycle and the write data does not get
forwarded to system memory via the write buffer. The GMCH/MCH provides the response and
HTRDY# for all Interrupt Message cycles including the ones originating from the GMCH/MCH.
The GMCH/MCH also supports interrupt re-direction for upstream interrupt memory writes.
For message based interrupts, system write buffer coherency is maintained by relying on strict
ordering of Memory Writes. The GMCH/MCH ensure that all Memory Writes received from a
given interface prior to an interrupt message Memory Write are delivered to the system bus for
snooping in the same order that they occur on the given interface.
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