Datasheet

Intel® 852GME GMCH and 852PM MCH Strap Pins
R
Datasheet 241
8 Intel
®
852GME GMCH and 852PM
MCH Strap Pins
8.1 Strapping Configuration Table
Table 60. Strapping Signals and Configuration
Pin Name Strap Description Configuration I/F Type Buffer Type
LCLKCTLB CPU Strap *Low=(default)
High = Mobile Intel
Pentium 4 processor
/Intel Celeron
processor
GPIO OUT
HSYNC XOR Chain Test Low = Normal Ops
(Default)
High = XOR Test On
GPIO OUT
VSYNC ALL Z Test Low = Normal Ops
(Default)
High = AllZ Test On
GPIO OUT
DVODETECT
§
DVO Select (If
DVODETECT=0 during
Reset, ADDID[7:0] is
latched to the ADDID
Register)
Low = DVO (Default) DVO BI
GPAR DVO/AGP Select
(Reserved)
Low = DVO (Default)
High = AGP
AGP BI
GSBA[7:0] 8-bit ADD Identifier
Straps
SBA[0] = ID Bit_0 …
SBA[7] = ID Bit_7
No default AGP IN
GST[2]
Note: Intel
852GME
GMCH Only
§
Clock Config: Bit_2
FSB 400 = 0
FSB 533 = 1
]; DVO Hi-Z
§
External pull-ups/downs will be required on the board to enable the non-default state of
the straps.
§