Datasheet

Overview
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24 Datasheet
within the Graphics Aperture address range pass through an address translation mechanism with a
fully associative 20 entry TLB. Accesses between AGP and hub interface are limited to memory
writes originating from the hub interface destined for AGP. The AGP interface is clocked from a
dedicated 66 MHz clock (GLCKIN). The AGP-to-host/core interface is asynchronous.
The AGP interface should be powered-off or tri-stated without voltage on the interface during
ACPI S3 or APM Suspend to RAM state.
Refer to the AGP Busy and Stop Signals Specification for more information.
1.8 Hub Interface
A proprietary interconnect connects the GMCH/MCH to the ICH4-M chipset. All communication
between the GMCH/MCH and the ICH4-M occur over the hub interface. The hub interface runs
at 66 MHz or 266 MB/s.
1.9 Address Decode Policies
Host initiated I/O cycles are positively decoded to the GMCH/MCH configuration space and
subtractively decoded to hub interface. Host initiated system memory cycles are positively
decoded to DDR SDRAM and are again subtractively decoded to hub interface if under 4 GB.
System memory accesses from hub interface to DDR SDRAM will be snooped on the FSB.
1.10 Platform Clocking
The GMCH/MCH has the following clock input/output pins:
• 400 MHz, Spread Spectrum, Low Voltage Differential BCLK, BCLK# for processor system
bus
• 533 MHz Spread Spectrum, Low Voltage Differential BCLK, BCLK# for processor system
bus (Intel 852GME GMCH and Intel 852PM MCH only)
• 66 MHz Spread Spectrum, 3.3 V GCLKIN for AGP and hub interface buffers
• Four pairs of differential output clocks (SCK[4,3,1:0], SCK[4,3,1:0]#), 200/266 MHz, 2.5 V
for system memory interface
• 48 MHz, non-Spread Spectrum, 3.3 V DREFCLK for the Display Frequency Synthesis
• 48 MHz or 66 MHz, Spread Spectrum, 3.3 V DREFSSCLK for the Display Frequency
Synthesis
• Up to 85 MHz, 1.5 V DVOBCCLKINT for TV-Out mode
• DPMS clock for S1-M
Clock Synthesizer chip(s) are responsible for generating the system host clocks, display and hub
interface clocks, PCI clocks, and system memory clocks. The host target speed is 400 MHz or 533
MHz. The GMCH does not require any relationship between the BCLK host clock and the 66
MHz clock generated for the AGP and hub interface; they are asynchronous to each other. The