Datasheet

Overview

Datasheet 23

The GMCH has four display ports, one analog and three digital. These provide support for a

progressive scan analog monitor, a dedicated dual channel LVDS panel and two DVO devices.

The data that is sent out to the display port is selected from one of the two possible sources, pipe

A or pipe B.

1.6.1 GMCH Analog Display Port

Intel 852GME GMCH has an integrated 350 MHz, 24-bit RAMDAC that can directly drive a

progressive scan analog monitor pixel resolution up to 1600x1200 at 85-Hz refresh and up to

2048x1536 at 75-Hz refresh. The DAC port can be driven on Pipe A or Pipe B.

1.6.2 GMCH Integrated LVDS Port

The Intel 852GME GMCH has an integrated dual channel LFP Transmitter interface to support

LVDS LCD panel resolutions up to UXGA with center and down spread SSC support of 0.5%,

1%, and 2.5% utilizing an external SSC clock.

The display pipe provides panel up-scaling to fit a source image into a specific panel size as well

as panning and centering support. The LVDS port is only supported on Pipe B. The LVDS port

can only be driven on Pipe B, either independently or simultaneously with the DAC port.

1.6.3 GMCH Integrated DVO Port

The DVO B/C interfaces are compliant with the DVI Specification 1.0. When combined with a

DVI compliant external device (e.g. TMDS Flat Panel Transmitter, TV-out encoder, etc.), the

GMCH provides a high-speed interface to a digital or analog display (e.g. flat panel, TV monitor,

etc.).

Intel 852GME GMCH provides a DVO B and DVO C port that are each capable of driving a 165

MHz pixel clock. When DVO B and DVO C are combined, the effective dot clock can be

increased to 330 MHz to support a dual channel (12-bit per channel) TV-Out Encoder. The DVO

B/C ports can be driven on Pipe A or Pipe B. If driven on port B, then the LVDS port must be

disabled.

1.7 External AGP Graphics Interface

1.7.1 Intel

852PM MCH and Intel

852GME GMCH AGP Interface

A single AGP component is supported by the AGP interface. The AGP buffers operate only in

1.5 V mode. They are not 3.3 V safe.

The AGP interface supports 1X/2X/4X AGP signaling and 2X/4X Fast Writes. AGP semantic

cycles to DDR SDRAM are not snooped on the host bus. PCI semantic cycles to DDR SDRAM

are snooped on the host bus. The GMCH/MCH support PIPE# or SBA[7:0] AGP address

mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be

selected during system initialization. Both upstream and downstream addressing is limited to 32-

bits for AGP and AGP/PCI transactions. The GMCH/MCH contains a 32-deep AGP request

queue. High priority accesses are supported. All accesses from the AGP/PCI interface that fall