Datasheet

Testability
R
Datasheet 225
7 Testability
In the Intel 852GME GMCH and Intel 852PM MCH, testability for Automated Test Equipment
(ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of
XOR gates, each with one input pin connected to it. The XOR Chain test mode is used by product
engineers during manufacturing and OEMs during board level connectivity tests. The main
purpose of this test mode is to detect connectivity shorts between adjacent pins and to check
proper bonding between I/O pads and I/O pins.
Figure 13. XOR-Tree Chain
The algorithm used for in–circuit test is as follows:
1. Drive all input pins to an initial logic level 1. Observe the output corresponding to scan chain
being tested.
2. Toggle pins one at a time starting from the first pin in the chain, continuing to the last pin,
from its initial logic level to the opposite logic level. Observe the output changes with each
pin toggle.
7.1 XOR Chain Differential Pairs
Table 55 provides differential signals in the XOR chains that must be treated as pairs. Pin1and
Pin2 as shown need to always drive to the opposite value.
Table 55. Differential Signals in the XOR Chains
Pin1 Pin2 XOR Chain
DVOCCLK# DVOCCLK DVO XOR 2
HLSTB# HLSTB HUB XOR