Datasheet

Overview
R
22 Datasheet
Table 1. SDRAM Memory Capacity
Technology Width System Memory
Capacity
System Memory
Capacity with High
Density
128 Mb 16 256 MB -
256 Mb 16 512 MB -
512 Mb 16 1 GB -
128 Mb 8 256 MB 512 MB
256 Mb 8 512 MB 1 GB
512 Mb 8 1 GB 2 GB
The Intel 852PM MCH and Intel 852GME system memory interface supports a thermal throttling
scheme to selectively throttle reads and/or writes. Throttling can be triggered either by on-die
thermal sensor, or by preset write bandwidth limits. Read throttle can also be triggered by an
external input pin. The memory controller logic supports aggressive dynamic row power down
features (SCKE) to help reduce power and supports Address and Control lines tri-stating when
DDR SDRAM is in active power down or self refresh.
The system memory architecture is optimized to maintain open pages (up to 16-kB page size)
across multiple rows. As a result, up to 16 pages across four rows. To complement this, the
GMCH will tend to keep pages open within rows, or will only close a single bank on a page miss.
Intel 852PM MCH and Intel 852GME support only two bank memory technologies.
The Intel 852GME GMCH and Intel 852PM MCH allow the memory interface to provide
optional ECC error checking for DDR SDRAM data integrity. During DDR SDRAM writes, ECC
is generated on a QWORD (64-bit) basis. Because the GMCH/MCH stores only entire cache lines
in its internal buffers, partial QWORD writes initially cause a read of the underlying data, and the
write-back into memory is no different from that of a complete cache line. During DDR SDRAM
reads and the read of the data that underlies partial writes, the GMCH/MCH supports detection of
single-bit and multiple-bit errors, and will correct single bit errors when correction is enabled.
1.6 GMCH Internal Graphics Interface
The GMCH provides a highly integrated graphics accelerator delivering high performance 3D,
2D, and video capabilities. With its interfaces to UMA using a DVMT configuration, analog
display, LVDS, and digital display (e.g. flat panel), the GMCH provides a complete graphics
solution.
The GMCH also provides 2D hardware acceleration for block transfers of data (BLTs). The BLT
engine provides the ability to copy a source block of data to a destination and perform raster
operations (e.g., ROP1, ROP2, and ROP3) on the data using a pattern, and/or another destination.
Performing these common tasks in hardware reduces processor load, and thus improves
performance.
High bandwidth access to data is provided through the system memory ports. The GMCH uses
Tiling architecture to increase system memory efficiency and thus maximize effective rendering
bandwidth.