Datasheet

Electrical Characteristics
R
Datasheet 213
6.4 Signal Groups
The signal description includes the type of buffer used for the particular signal:
Signal Description
AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete
details. The GMCH/MCH integrates AGTL+ termination resistors. AGTL+ signals are
“inverted bus” style where a low voltage represents a logical 1.
DVO/AGP DVO/AGP buffers (1.5 V tolerant)
Hub Compatible to Hub Interface 1.5
SSTL_2 Stub Series Termination Logic compatible signals (2.5 V tolerant)
LVTTL Low Voltage TTL compatible signals (3.3 V tolerant)
CMOS CMOS buffers (3.3 V tolerant)
LVDS Low Voltage Differential Signal interface
Analog Analog signal interface
Ref Voltage reference signal
Table 51. Signal Groups
Signal
Group
Signal Type Signals Notes
Host Interface Signal Groups
(a) AGTL+
Input/Outputs
ADS#, BNR#, BREQ0#,DBSY#, DRDY#, DINV[3:0]#,
HA[31:3]#, HADSTB[1:0]#, HD[63:0]#,HDSTBP[3:0]#,
HDSTBN[3:0]#, HIT#, HITM#, HREQ[4:0]#, HLOCK#
(b) AGTL+
Common Clock
Outputs
BPRI#, CPURST#, DEFER#, HTRDY#, RS[2:0]#,
DPWR#
(d) Analog/Ref
Host Miscellaneous
Signals
HAVREF, HCCVREF, HDVREF[2:0], HXSWING,
HYSWING, HXRCOMP, HYRCOMP
(c) AGTL+
Asynchronous Input
HLOCK#, DPSLP#
DVO Signal Groups
(e) DVO
Inputs
DVOBCCLKINT, DVOCFLDSTL, DVOBCINTR#,
DVOBFLDSTL, ADDID[7:0], DVODETECT
(f) DVO
Outputs
DVOCD[11:0], DVOCHSYNC, DVOCVSYNC,
DVOCBLANK#, DVOBD[11:0], DVOBHSYNC,
DVOBVSYNC, DVOBBLANK#
(e),(f) DVO
DDC/I
2
C Input/Output
MI2CCLK, MI2CDATA, MDVICLK, MDVIDATA,
MDDCDATA, MDDCCLK