Datasheet

Overview

Datasheet 21

1.4 Processor Host Interface

Intel 852GME GMCH and 852PM MCH are optimized for the Mobile Intel Pentium 4 processor.

The key features are:

• Source synchronous double pumped address (2X)

• Source synchronous quad pumped data (4X)

• System Bus interrupt and side-band signal delivery

• A System Bus frequency of 400/533 MHz (Dual processor is not supported)

• AGTL+ termination resistors on all of the AGTL+ signals

• 32-bit host bus addressing allowing the CPU to access the entire 4 GB of the memory address

space

The GMCH/MCH has a 12-deep In-Order Queue to support up to twelve outstanding pipelined

address requests on the host bus. The GMCH/MCH supports one outstanding defer cycle at a

time; however, it supports only one to any particular I/O interface. Host initiated I/O cycles are

positively decoded to the GMCH/MCH configuration space and subtractively decoded to the hub

interface. Host initiated memory cycles are positively decoded to DDR SDRAM. Memory

accesses initiated from the hub interface to DDR SDRAM will be snooped on the System Bus.

Host initiated I/O cycles are decoded to AGP/PCI1, hub interface, or GMCH/MCH configuration

space. Host initiated memory cycles are decoded to AGP/PCI1, hub interface, system memory.

All memory accesses from the FSB that hit the graphics aperture are translated using an AGP

address translation table. The GMCH/MCH access to graphics memory and AGP/PCI1 device

accesses to non-cacheable system memory are not snooped on the FSB. Memory accesses

initiated from AGP/PCI1 using PCI semantics and from hub interface to system memory will be

snooped on the host bus.

1.4.1 Host Bus Error Checking

The Intel 852GME GMCH and Intel 852PM MCH do not generate nor check parity for Data,

Address/Request, and Response signals on the processor bus.

1.5 Intel

852PM and 852GME DDR SDRAM Interface

The System Memory controller directly supports the following:

• One channel of PC1600/2100 SO-DIMM DDR SDRAM memory

• DDR SDRAM devices with densities of 128-Mbit, 256-Mbit, and 512-Mbit technology

• Maximum system memory support of two, double-sided SO-DIMMs (four rows populated)

with up to 2 GB memory

• Variable page sizes of 2 kB, 4 kB, 8 kB, and 16 kB. Page size is individually selected for

every row and a maximum of 16 pages may be opened simultaneously 2 GB of memory

support is realized by utilizing a high density memory configuration.