Datasheet

Functional Description
R
204 Datasheet
All other accesses that do not correspond to this programmed address range are forwarded to
the hub interface.
• Exclusive Access. GMCH/MCH does not issue a locked cycle on the AGP bus on behalf of
either the host or the hub interface. The hub interface and host locked transactions to AGP
are initiated as unlocked transactions by the GMCH/MCH on the AGP bus.
• Configuration Read and Write. Host Configuration cycles to AGP are forwarded as Type 1
Configuration Cycles.
• Fast Back-to-Back Transactions. GMCH/MCH as an initiator does not perform fast back-to-
back cycles.
GMCH Retry/Disconnect Conditions
The GMCH generates retry/disconnect according to the AGP Specification rules when being
accessed as a target from the AGP FRAME# device.
Delayed Transaction
When an AGP FRAME#-to-DRAM read cycle is retried by the GMCH, it is processed internally
as a Delayed Transaction.
The GMCH/MCH supports the Delayed Transaction mechanism on the AGP target interface for
the transactions issued using AGP FRAME# protocol. This mechanism is compatible with the
PCI 2.1 Specification. The process of latching all information required to complete the
transaction, terminating with Retry, and completing the request without holding the master in
wait-states is called a Delayed Transaction. The GMCH/MCH latches the Address and Command
when establishing a Delayed Transaction. The GMCH/MCH generates a Delayed Transaction on
the AGP only for AGP FRAME# to DRAM read accesses. The GMCH/MCH does not allow
more than one Delayed Transaction access from AGP at any time.
5.7 Power and Thermal Management
The Intel 852GME GMCH and Intel 852PM MCH are intended to be compliant with the
following specifications and technologies:
• APM Rev 1.2
• PCI Power Management Rev 1.0
• PC’99, Rev 1.0, PC’99A, and PC’01, Rev 1.0
• ACPI 1.0b and 2.0 support
• ACPI S0, S1-M, S3, S4, S5, C0, C1, C2, C3 states
• Internal Graphics Adapter D0, D1, D3 (Hot/Cold)
• On Die Thermal sensor, enabling core and system memory write thermal throttling for
prevention of catastrophic thermal conditions
• External Thermal sensor input pin
• Enabling SO-DIMM Thermal throttling