Datasheet

Functional Description
R
Datasheet 203
GMCH/MCH
PCI
Command
C/BE[3:0]#
Encoding
Cycle Destination
Response as A FRAME#
Target
Configuration
Write
1011 N/A No Response
Memory
Read Multiple
1100 Main Memory Read
1100 The hub interface No Response
Dual Address
Cycle
1101 N/A No Response
Memory
Read Line
1110 Main Memory Read
1110 The hub interface No Response
Memory
Write and
Invalidate
1111 Main Memory Posts Data
1111 The hub interface No Response
NOTE: N/A refers to a function that is not applicable.
As a target of an AGP FRAME# cycle, the GMCH/MCH only supports the following
transactions:
• Memory Read, Memory Read Line, and Memory Read Multiple. These commands are
supported identically by the GMCH/MCH. The GMCH/MCH does not support reads of the
hub interface bus from AGP.
• Memory Write and Memory Write and Invalidate. These commands are aliased and processed
identically. The GMCH/MCH does not support writes to the hub interface bus from AGP.
• Other Commands. Other commands such as I/O R/W and Configuration R/W are not
supported by the GMCH as a target and result in master abort.
• Exclusive Access. The GMCH/MCH does not support PCI locked cycles as a target.
• Fast Back-to-Back Transactions. GMCH/MCH as a target supports fast back-to-back cycles
from an AGP FRAME# initiator.
As an initiator of AGP FRAME# cycle, the GMCH/MCH only supports the following
transactions:
• Memory Read and Memory Read Line. GMCH/MCH supports reads from host to AGP.
GMCH/MCH does not support reads from the hub interface to AGP.
• Memory Read Multiple. This command is not supported by the GMCH/MCH as an AGP
FRAME# initiator.
• Memory Write. GMCH/MCH initiates AGP FRAME# cycles on behalf of the host or the hub
interface. GMCH/MCH does not issue Memory Write and Invalidate as an initiator.
GMCH/MCH does not support write merging or write collapsing. GMCH/MCH allows non-
snoopable write transactions from the hub interface to the AGP bus.
• I/O Read and Write. I/O read and write from the host are sent to the AGP bus. I/O base and
limit address range for AGP bus are programmed in AGP FRAME# configuration registers.