Datasheet

Functional Description
R
202 Datasheet
Table 45. Fast Write Initialization
FWEN DATA_RATE [2] DATA_RATE [1] DATA_RATE
[0]
GMCH =>AGP Master
Write Protocol
0 X x x 1X
1 0 0 1 1X
1 0 1 0 2X Strobing
1 1 0 0 4X Strobing
5.6.4.2 AGP FRAME# Transactions on AGP
The GMCH/MCH accepts and generates AGP FRAME# transactions on the AGP bus. The
GMCH/MCH guarantees that AGP FRAME# accesses to DRAM are kept coherent with the
processor caches by generating snoops to the host bus. LOCK#, SERR#, and PERR# signals are
not supported.
GMCH/MCH Initiator and Target Operations
Table 54 summarizes GMCH/MCH target operation for AGP FRAME# initiators. The cycles can
be either destined for main memory or the hub interface.
Table 46. PCI Commands Supported by the GMCH/MCH When Acting as a FRAME# Target
GMCH/MCH
PCI
Command
C/BE[3:0]#
Encoding
Cycle Destination
Response as A FRAME#
Target
Interrupt
Acknowledge
0000 N/A No Response
Special Cycle 0001 N/A No Response
I/O Read 0010 N/A No Response
I/O Write 0011 N/A No Response
Reserved 0100 N/A No Response
Reserved 0101 N/A No Response
Memory
Read
0110 Main Memory Read
0110 The hub interface No Response
Memory
Write
0111 Main Memory Posts Data
0111 The hub interface No Response
Reserved 1000 N/A No Response
Reserved 1001 N/A No Response
Configuration
Read
1010 N/A No Response