Datasheet

Functional Description
R
Datasheet 201
5.6.4 4X AGP Protocol
In addition to the 1X and 2X AGP protocol, the GMCH/MCH supports 4X AGP read and write
data transfers and 4X sideband address generation. The 4X operation is compliant with the AGP
2.0 specification.
The GMCH/MCH indicates that it supports 4X data transfers through RATE[2] (bit 2) of the AGP
Status Register. When DATA_RATE[2] of the AGP Command Register is set to 1 during system
initialization, the GMCH/MCH performs AGP read/write data transactions using 4X protocol.
This bit is not dynamic. Once this bit is set during initialization, the data transfer rate will not
change.
The 4X data rate transfer provides 1.06 GB/s transfer rates. The control signal protocol for the 4X
data transfer protocol is identical to 1X/2X protocol. In 4X mode 16 bytes of data are transferred
on every 66 MHz clock edge. The minimum throttleable block size remains four 66 MHz clocks,
which means 64 bytes of data are transferred per block. Three additional signal pins are required
to implement the 4X data transfer protocol. These signal pins are complementary data transfer
strobes for the AD bus (2) and the SBA bus (1).
5.6.4.1 Fast Writes
The GMCH/MCH supports 2X and 4X Fast Writes from the GMCH/MCH to the graphics
controller on AGP. The Fast Write operation is compliant with the AGP 2.0 specification.
The GMCH/MCH will not generate Fast Back to Back (FB2B) cycles in 1X mode, but will
generate FB2B cycles in 2X and 4X Fast Write modes.
To use the Fast Write protocol, the Fast Write Enable configuration bit, AGPCMD[FWEN] (bit 4
of the AGP Command Register), must be set to 1.
Memory writes originating from the host or from the hub interface use the Fast Write protocol
when it is both capability enabled and enabled. The data rate used to perform the Fast Writes is
dependent on the bits set in the AGP Command Register bits 2:0 (DATA_RATE).
• If bit 2 of the AGPCMD[DATA_RATE] field is 1, the data transfers occur using 4X
strobing.
• If bit 1 of AGPCMD[DATA_RATE] field is 1, the data transfers occur using 2X strobing.
• If bit 0 of AGPCMD[DATA_RATE] field is 1, Fast Writes are disabled and data transfers
occur using standard PCI protocol.
Note that only one of the three DATA_RATE bits may be set by initialization software. This is
summarized in the following table.