Datasheet

Functional Description
R
200 Datasheet
GMCH/MCH Host Bridge Max
AGP
Command
C/BE[3:0]#
Encoding
Cycle
Destination
Response as PCIx Target
0100 The hub interface Cycle goes to DRAM with BE’s inactive; does
not go to the hub interface
Hi-Priority
Write
0101 Main Memory High Priority Write
0101 The hub interface Cycle goes to DRAM with BE’s inactive; does
not go to the hub interface
Reserved 0110 N/A No Response
Reserved 0111 N/A No Response
Long Read 1000 Main Memory Low Priority Read
The hub interface Complete locally with random data; does not
go to the hub interface
Hi-Priority
Long Read
1001 Main Memory High Priority Read
The hub interface Complete locally with random data; does not
go to the hub interface
Flush 1010 GMCH Complete with QW of Random Data
Reserved 1011 N/A No Response
Fence 1100 GMCH No Response - Flag inserted in GMCH request
queue
Reserved 1101 N/A No Response
Reserved 1110 N/A No Response
Reserved 1111 N/A No Response
NOTE: N/A refers to a function that is not applicable.
As a target of an AGP cycle, the GMCH/MCH supports all the transactions targeted at main
memory (summarized in the table above). The GMCH/MCH supports both normal and high-
priority read and write requests. The GMCH/MCH does not support AGP cycles to the hub
interface. PIPE# and SBA cycles are assumed not to require coherency management and all AGP
initiator accesses to main memory using AGP PIPE# or SBA protocol are treated as non-
snoopable cycles. These accesses are directed to the AGP aperture in main memory that is
programmed as either uncacheable (UC) memory or write combining (WC) in the processor’s
MTRRs.
5.6.2 AGP Transaction Ordering
The GMCH observes transaction ordering rules as defined by the AGP Interface Specification Rev
2.0.
5.6.3 AGP Signal Levels
The GMCH/MCH supports 1X/2X/4X data transfers using 1.5 V signaling levels.