Datasheet

Functional Description

Datasheet 197

5.5.2.8 SSC Support

The GMCH is designed to tolerate a 0.6%-2.5% down/center spread at a modulation rate range

from 30-50 kHz triangle. By using an external SSC clock synthesizer to provide the 66 MHz

reference clock into the GMCH Pipe B PLL, spectrally spread 7X, 3.5X, and 1X LVDS clocking

is output from the GMCH Pipe B PLL.

5.5.2.9 Panel Power Sequencing

This section provides details for the power sequence timing relationship of the panel power, the

backlight enable and the LVDS data timing delivery. In order to meet the panel power timing

specification requirements, two signals, PANELVDDEN

and PANELBKLTEN are provided to

control the timing sequencing function of the panel and the backlight power supplies.

5.5.2.9.1 Panel Power Sequence States

A defined power sequence is recommended when enabling the panel or disabling the panel. The

set of timing parameters can vary from panel to panel vendor, provided that they stay within a

predefined range of values. The panel VDD power, the backlight on/off state and the LVDS clock

and data lines are all managed by an internal power sequencer.

A requested power-up sequence is only allowed to begin after the power cycle delay time

requirement T4 is met. This is programmed in the Power Cycle Delay bits (Panel Power Cycle

Delay and Reference Divider Register address offset 61210-61213h, bits 0-4).

Figure 12. Panel Power Sequencing