Datasheet

Functional Description
R
196 Datasheet
Figure 11. LVDS Clock and Data Relationship
LVDS Clock and data
7th
data
1st
data
2nd
data
3rd
data
4th
data
5th
data
6th
data
7th
data
1st
data
1 1 1 0 0 0 1 1 1
LVDS Clock Pair
LVDS Data Pair
5.5.2.4 LVDS Pair States
The LVDS pairs can be put into one of five states: powered down tri-state, powered down Zero
Volts, common mode, send zeros, or active. When in the active state, several data formats are
supported. When in powered down state, the circuit enters a low power state and drives out 0 V or
tri-states on both the output pins for the entire channel. The common mode tri-state is both pins of
the pair set to the common mode voltage. The common mode state only occurs on B3, A3, or
CLKB. These are the signals that optionally get used when driving either 18-bpp panels or dual
channel with a single clock. When in the send zeros state, the circuit is powered up but sends only
zero for the pixel color data regardless of what the actual data is with the clock lines and timing
signals sending the normal clock and timing data.
5.5.2.5 Single Channel versus Dual Channel Mode
Both single channel and dual channel modes are available to allow interfacing to either single or
dual channel panel interfaces. This LVDS port can operate in single channel or dual channel
mode. Dual channel mode uses twice the number of LVDS pairs and transfers the pixel data at
twice the rate of the single channel. In general, one channel will be used for even pixels and the
other for odd pixel data. The first pixel of the line is determined by the display enable going
active and that pixel will be sent out channel A. All horizontal timings for active, sync, and blank
will be limited to two pixel boundaries in the two channel modes.
5.5.2.6 LVDS Channel Skew
When in dual channel mode, the two channels must meet the panel requirements with respect to
the inter-channel skew.
5.5.2.7 LVDS PLL
The Display PLL is used to synthesize the clocks that control transmission of the data across the
LVDS interface. The three operations that are controlled are the pixel rate, the load rate, and the
IO shift rate. These are synchronized to each other and have specific ratios based on single
channel or dual channel mode. If the pixel clock is considered the 1x rate, a 7x or 3.5x speed
IO_shift clock is needed for the high speed serial outputs setting the data rate of the transmitters.
The load clock will have either a 1x or .5x ratio to the pixel clock.