Datasheet

Functional Description

180 Datasheet

The above table is only a subset of the defined SPD bytes on the SO-DIMMs. These bytes

collectively provide enough data for programming the GMCH/MCH DDR SDRAM registers.

5.3.3 DDR SDRAM Performance Description

The overall system memory performance is controlled by the DDR SDRAM timing register,

pipelining depth used in GMCH/MCH, system memory speed grade and the type of DDR

SDRAM used in the system. Besides this, the exact performance in a system is also dependent on

the total system memory supported, external buffering and system memory array layout. The most

important contribution to overall performance by the system memory controller is to minimize the

latency required to initiate and complete requests to system memory, and to support the highest

possible bandwidth (full streaming, quick turn-arounds). One measure of performance is the total

flight time to complete a cache line request. A true discussion of performance really involves the

entire chipset, not just the system memory controller.

5.3.4 Intel

852GME GMCH and Intel

852PM MCH Data Integrity

(ECC)

The GMCH/MCH supports single-bit Error Correcting Code (or Error Checking and Correcting)

(ECC) and multiple-bit Error Checking (EC) on the main memory interface. The GMCH/MCH

generates an 8-bit code word for each 64-bit Qword of memory. GMCH/MCH performs two

Qword writes at a time so two 8-bit codes are sent with each write. Since the code word covers a

full Qword, writes of less than a Qword require a read-merge-write operation. Consider a Dword

write to memory. In this case, when in ECC mode, GMCH/MCH will read the Qword where the

addressed Dword will be written, merge in the new Dword, generate a code covering the new

Qword and finally write the entire Qword and code back to memory. Any correctable (single-bit)

errors detected during the initial Qword read are corrected before merging the new Dword. The

GMCH/MCH also supports another data integrity mode, EC mode. In this mode, the

GMCH/MCH generates and stores a code for each Qword of memory. It then checks the code for

reads from memory but does not correct any errors that are found.

5.4 Integrated Graphics Overview

The GMCH provides a highly integrated graphics accelerator and PCI set while allowing a

flexible integrated system graphics solution.