Datasheet

Overview
R
18 Datasheet
Term Description
DBL Display Brightness Link
DVO Digital Video Out
DVI* Digital Visual Interface is the interface specified by the DDWG (Digital Display
Working Group) DVI Spec. Rev. 1.0 utilizing only the Silicon Image developed
TMDS protocol
DVMT Dynamic Video Memory Technology
EDID Extended Display Identification Data
Full Reset A Full GMCH Reset is defined in this document when RSTIN# is asserted
GMCH Graphics and Memory Controller Hub
Hub Interface (HI) The proprietary interconnect between the GMCH and the ICH4-M component. In
this document, the hub interface cycles originating from or destined for the ICH4-M
are generally referred to as “hub interface cycles.” Hub cycles originating from or
destined for the primary PCI interface on are sometimes referred to as “hub
interface/PCI cycles”
Host This term is used synonymously with processor
IGD Integrated Graphics Device
Intel
®
852GME GMCH Refers to the GMCH component. Throughout this datasheet, the Intel /852GME
GMCH will be referred to as the GMCH.
Intel
®
852PM MCH Refers to the MCH component. Throughout this datasheet, the Intel 852PM MCH
will be referred to as the MCH.
Intel
®
852 chipset
Family
Refers to both 852GME and 852PM chipset.
Intel
®
82801DBM ICH4-
M
The component contains the primary PCI interface, LPC interface, USB 2.0, ATA-
100, AC’97, and other I/O functions. It communicates with the GMCH over a
proprietary interconnect called the hub interface. Throughout this datasheet, the
Intel
®
82801DBM ICH4-M component will be referred to as the ICH4-M
IPI Inter Processor Interrupt
LFP Local Flat Panel
LVDS Low Voltage Differential Signals used for interfacing to LCD Flat Panels
MSI Message Signaled Interrupts. MSI allow a device to request interrupt service via a
standard memory write transaction instead of through a hardware signal
FSB Front Side Bus. Connection between GMCH and the CPU. Also known as the
Host interface
PWM Pulse Width Modulation
SSC Spread Spectrum Clocking