Datasheet

Functional Description
R
Datasheet 179
5.3.2 Memory Organization and Configuration
5.3.2.1 Configuration Mechanism for SO-DIMMs
Detection of the type of DDR SDRAM installed on the SO-DIMM is supported via Serial
Presence Detect mechanism as defined in the JEDEC 200-pin SO- DIMM specification.
Before any cycles to the system memory interface can be supported, the GMCH/MCH DDR
SDRAM registers must be initialized. The GMCH/MCH must be configured for operation with
the installed system memory types. Detection of system memory type and size is done via the
System Management Bus (SMB) interface on the ICH4-M. This two-wire bus is used to extract
the DDR SDRAM type and size information from the Serial Presence Detect port on the DDR
SDRAM SO-DIMMs.
DDR SDRAM SO-DIMMs contain a 5-pin Serial Presence Detect interface, including SCL (serial
clock), SDA (serial data) and SA[2:0]. Devices on the SMBus have a 7-bit address. For the DDR
SDRAM SO-DIMMs, the upper four bits are fixed at 1010. The lower three bits are strapped on
the SA[2:0] pins. SCL and SDA are connected directly to the system management bus on the
ICH4-M. Thus data is read from the Serial Presence Detect port on the SO-DIMMs via a series of
I/O cycles to the south bridge. The BIOS needs to determine the size and type of system memory
used for each of the rows of system memory in order to properly configure the GMCH/MCH
system memory interface.
For SMBus Configuration and Access of the Serial Presence Detect Ports, refer to the Intel
®
82801DBM I/O Controller Hub 4 Mobile (ICH4-M) Datasheet (252337-001) for more detail.
5.3.2.2 System Memory Register Programming
This section provides summary of how the required information for programming the DDR
SDRAM registers is obtained from the Serial Presence Detect ports on the SO-DIMMs. The
Serial Presence Detect ports are used to determine Refresh Rate, MA and MD Buffer Strength,
Row Type (on a row by row basis), DDR SDRAM timings, row sizes and row page sizes. The
following table lists a subset of the data available through the on board Serial Presence Detect
ROM on each SO-DIMM.
Table 41. Data Bytes on SO-DIMM Used for Programming DDR SDRAM Registers
Byte Description
2 System Memory Type (DDR SDRAM)
3 Number of Row Addresses, not counting Bank Addresses
4 Number of Column Addresses
5 Number of SO-DIMM banks
11 ECC, No ECC
12 Refresh Rate/Type
17 Number Banks on each Device