Datasheet

Functional Description

178 Datasheet

PCI bus instead of asserting a hardware signal to the IOxAPIC. The MSI may be directed to the

IOxAPIC, which in turn generates an interrupt as an upstream hub interface Memory Write.

Alternatively the MSI may be directed directly to the system bus. The target of an MSI is

dependent on the address of the interrupt Memory Write. The GMCH forwards inbound hub

interface Memory Writes to address 0FEEx_xxxxh, to the System Bus as “Interrupt Message

Transactions”.

5.2.2 Upstream Interrupt Messages

The GMCH/MCH accepts message based interrupts from its hub interface and forwards them to

the System Bus as Interrupt Message Transactions. The interrupt messages presented to the

GMCH/MCH are in the form of Memory Writes to address 0FEEx_xxxxh. At the hub interface,

the Memory Write interrupt message is treated like any other Memory Write; it is either posted

into the inbound data buffer (if space is available) or retried (if data buffer space is not

immediately available). Once posted, the Memory Write from the hub interface, to address

0FEEx_xxxxh, is decoded as a cycle that needs to be propagated by the GMCH/MCH to the

System Bus as an Interrupt Message transaction.

5.3 System Memory Interface

5.3.1 DDR SDRAM Interface Overview

The Intel 852GME GMCH and Intel 852PM MCH support DDR SDRAM at 200/266/333 MHz,

respectively. The GMCH/MCH includes support for:

• Up to 2-GB of PC2100/2700 DDR SDRAM

• PC2100/2700 unbuffered 200-pin DDR SO-DIMMs

• Maximum of 2 SO-DIMMs, single-sided and/or double-sided/or stacked

The 2-bank select lines SBA[1:0] and the 13 Address lines SMA[12:0] allow the GMCH/MCH to

support 64-bit wide SO-DIMMs using 128-Mb, 256-Mb, and 512-Mb DDR SDRAM technology.

While address lines SMA[9:0] determine the starting address for a burst, burst lengths can be 4 or

8. Four chip selects SCS[3:0]# lines allow a maximum of two rows of single-sided DDR SDRAM

SO-DIMMs and four rows of double-sided DDR SDRAM SO-DIMMs.

The GMCH/MCH main memory controller targets CAS latencies of 2 and 2.5 for DDR SDRAM.

The GMCH/MCH provides refresh functionality with a programmable rate (normal DDR

SDRAM rate is 1 refresh/15.6 µs). For write operations of less than a full cache line, the

GMCH/MCH will perform a cache-line read and into the write buffer and perform byte-wise

write-merging in the write buffer.