Datasheet

Functional Description

Datasheet 177

5 Functional Description

5.1 Host Interface Overview

The processor system bus uses source synchronous transfers for the address and data signals. The

address signals are double pumped and two addresses can be generated every bus clock. At 100

MHz bus frequency, the two address signals run at 200 MT/s for a maximum address queue rate

of 50 M addresses/sec. The data is quad pumped and an entire 64 bits cache line can be

transferred in two bus clocks. At 133 MHz bus frequency, the data signals run at 533-MT/s for a

maximum bandwidth of 4.3-GB/s.

5.2 Dynamic Bus Inversion

The GMCH/MCH supports Dynamic Bus Inversion (DBI) when driving and receiving data from

the Host bus. DBI limits the number of data signals that are driven to a low voltage on each quad

pumped data phase. This decreases the power consumption of the GMCH/MCH. DINV[3:0]

indicates if the corresponding 16 bits of data are inverted on the bus for each quad pumped data

phase:

Table 40. Relation of DBI Bits to Data Bits

DINV[3:0] Data Bits

DINV[0]# HD[15:0]#

DINV[1]# HD[31:16]#

DINV[2]# HD[47:32]#

DINV[3]# HD[63:48]#

Whenever the processor or the GMCH/MCH drive data, each 16-bit segment is analyzed. If more

than eight of the 16 data signals would normally be driven low on the bus the corresponding

DINV# signal will be asserted and the data will be inverted prior to being driven on the bus.

Whenever the CPU or the GMCH/MCH receive data, they monitor DINV[3:0]# to determine if

the corresponding data segment should be inverted.

5.2.1 System Bus Interrupt Delivery

Each processor supports system bus interrupt delivery. They do not support the APIC serial bus

interrupt delivery mechanism. Interrupt related messages are encoded on the System Bus as

“Interrupt Message Transactions.” System bus interrupts may originate from the processor on the

system bus, or from a downstream device on hub interface.

The ICH4-M contains IOxAPICs and its interrupts are generated as upstream hub interface

Memory Writes. Furthermore, PCI 2.2 defines MSI’s (Message Signaled Interrupts) that are also

in the form of Memory Writes. A PCI 2.2 device may generate an interrupt as an MSI cycle on its