Datasheet

System Address Map
R
Datasheet 175
If a cycle is outside of a valid main memory range then it will terminate as follows:
Reads: Remap to memory address 0h, return data from address 0h, and set the IAAF error flag.
Writes: Re-mapped to memory address 0h with BE’s de-asserted (effectively dropped “on the
floor”) and set the IAAF error flag.
AGP Accesses to GMCH/MCH that Cross Device Boundaries
For FRAME# accesses, when an AGP or PCI master gets disconnected it will resume at the new
address which allows the cycle to be routed to or claimed by the new target. Therefore accesses
should be disconnected by the target on potential device boundaries. The GMCH/MCH will
disconnect AGP/PCI transactions on 4-kB boundaries.
AGPPIPE# and SBA accesses are limited to 256 bytes and must hit DDR SDRAM. AGP accesses
are dispatched to DDR SDRAM on naturally aligned 32 - byte block boundaries. The portion of
the request that hits a valid address will complete normally. The portion of a read access that hits
an invalid address will be re-mapped to address 0h, return data from address 0h, and set the IAAF
error flag. The portion of a write access that hits an invalid address will be re-mapped to memory
address 0h with BE’s de-asserted (effectively dropped “on the floor”) and set the IAAF error flag.
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