Datasheet

System Address Map
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174 Datasheet
4.4.6.1.1 Hub Interface Accesses to GMCH/MCH that Cross Device Boundaries
Hub interface accesses are limited to 256-bytes but have no restrictions on crossing address
boundaries. A single hub interface request may therefore span device boundaries (AGP, DDR
SDRAM) or cross from valid addresses to invalid addresses (or vise versa). The GMCH/MCH
does not support transactions that cross device boundaries. For reads and for writes requiring
completion, the GMCH/MCH will provide separate completion status for each naturally aligned
32 -or 64 -byte block. If the starting address of a transaction hits a valid address, the portion of a
request that hits that target device (AGP or DDR SDRAM) will complete normally. The
remaining portion of the access that crosses a device boundary (targets a different device than that
of the starting address) or hits an invalid address will be remapped to memory address 0h,
snooped on the host bus, and dispatched to DDR SDRAM. Reads will return all 1’s with Master
Abort completion. Writes will have BEs deasserted and will terminate with Master Abort if
completion is required.
If the starting address of a transaction hits a invalid address the entire transaction will be re-
mapped to memory address 0h, snooped on the host bus, and dispatched to DDR SDRAM. Reads
will return all 1’s with Master Abort completion. Writes will have BEs deasserted and will
terminate with Master Abort if completion is required.
4.4.6.1.2 AGP Interface Decode Rules
Cycles Initiated Using PCI Protocol
The GMCH/MCH does not support any AGP/PCI access targeting hub interface. The GMCH will
claim AGP/PCI initiated memory read and write transactions decoded to the main DDR SDRAM
range or the Graphics Aperture range. All other memory read and write requests will be master-
aborted by the AGP/PCI initiator as a consequence of GMCH/MCH not responding to a
transaction.
Under certain conditions, the GMCH/MCH restricts access to the DOS Compatibility ranges
governed by the PAM registers by distinguishing access type and destination bus. The
GMCH/MCH accepts AGP/PCI write transactions to the compatibility ranges if the PAM
designates DDR SDRAM as write-able. If accesses to a range are not write-enabled by the PAM,
the GMCH/MCH does not respond and the cycle will result in a master-abort. The GMCH/MCH
accepts AGP/PCI read transactions to the compatibility ranges if the PAM designates DDR
SDRAM as readable. If accesses to a range are not read enabled by the PAM, the GMCH/MCH
do not respond and the cycle will result in a master-abort.
If agent on AGP/PCI issues an I/O or PCI Special Cycle transaction, the GMCH will not respond
and cycle will result in a master-abort. The GMCH will accept PCI configuration cycles to the
internal GMCH devices as part of the PCI configuration/co-pilot mode mechanism.
Cycles Initiated Using AGP Protocol
All cycles must reference main memory i.e. main DDR SDRAM address range (excluding PAM)
or Graphics Aperture range (also physically mapped within DDR SDRAM but using different
address range). AGP accesses to the PAM region from 640 kB to 1 MB are not allowed. AGP
accesses to SMM space are not allowed. AGP initiated cycles that target DDR SDRAM are not
snooped on the host bus, even if they fall outside of the AGP aperture range.