Datasheet

System Address Map
R
Datasheet 173
The GMCH/MCH positively decodes I/O accesses to AGP I/O address space as defined by the
following equation:
I/O_Base_Address ≤ CPU I/O Cycle Address ≤I/O_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration software and it
depends on the size of I/O space claimed by the AGP device.
The GMCH/MCH also forwards accesses to the Legacy VGA I/O ranges according to the settings
in the Device #1 configuration registers BCTRL (VGA Enable) and PCICMD1 (IOAE1), unless a
second adapter (monochrome) is present on the hub interface/PCI (or ISA). The presence of a
second graphics adapter is determined by the MDAP configuration bit. When MDAP is set, the
GMCH/MCH will decode legacy monochrome IO ranges and forward them to the hub interface.
The IO ranges decoded for the monochrome adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3Bah and
3BFh.
The GMCH/MCH Device #1 I/O address range registers defined above are used for all I/O space
allocation for any devices requiring such a window on AGP. These devices would include the
AGP device, PCI66 MHz/3.3 V agents, and multifunctional AGP devices where one or more
functions are implemented as PCI devices.
The PCICMD1 register can disable the routing of I/O cycles to the AGP.
4.4.6 GMCH Decode Rules and Cross-Bridge Address Mapping
The address map described above applies globally to accesses arriving on any of the three
interfaces i.e. Host bus, IGD, and hub interface or AGP.
4.4.6.1 Hub Interface Decode Rules
The GMCH/MCH accepts accesses from hub interface to the following address ranges:
• All memory read and write accesses to main DDR SDRAM including PAM region (except
SMM space)
• All memory read/write accesses to the Graphics Aperture (DDR SDRAM) defined by
APBASE and APSIZE.
• All hub interface memory write accesses to AGP memory range defined by MBASE,
MLIMIT, PMBASE, and PMLIMIT.
• Memory writes to VGA range on AGP if enabled.
All memory reads from the hub interface A that are targeted > 4-GB memory range will be
terminated with Master Abort completion, and all memory writes (>4-GB) from the hub interface
will be ignored.
Hub interface memory accesses that fall elsewhere within the memory range are considered
invalid and will be re-mapped to memory address 0h, snooped on the host bus, and dispatched to
DDR SDRAM. Reads will return all 1’s with Master Abort completion. Writes will have BEs
deasserted and will terminate with Master Abort if completion is required. I/O cycles will not be
accepted. They are terminated with Master Abort completion packets.