Datasheet

System Address Map
R
172 Datasheet
4.4.4 System Memory Shadowing
Any block of system memory that can be designated as Read-Only or Write-Only can be
“shadowed” into GMCH/MCH DDR SDRAM. Typically this is done to allow ROM code to
execute more rapidly out of main DDR SDRAM. ROM is used as a Read-Only during the copy
process while DDR SDRAM at the same time is designated Write-Only. After copying, the DDR
SDRAM is designated Read-Only so that ROM is shadowed. CPU bus transactions are routed
accordingly.
4.4.5 I/O Address Space
The GMCH/MCH does not support the existence of any other I/O devices beside itself on the
CPU bus. The GMCH/MCH generates hub interface or PCI bus cycles for all CPU I/O accesses
that it does not claim. Within the host bridge the GMCH/MCH contains two internal registers in
the CPU I/O space, Configuration Address register (CONFIG_ADDRESS) and the Configuration
Data register (CONFIG_DATA). These locations are used to implement Configuration Space
Access Mechanism and as described in the Configuration register section.
The processor allows 64-kB +3-B to be addressed within the I/O space. The GMCH/MCH
propagates the CPU I/O address without any translation on to the destination bus and therefore
provides addressability for 64-k+3-B locations. Note that the upper three locations can be
accessed only during I/O address wrap-around when CPU bus A16# address signal is asserted.
A16# is asserted on the CPU bus whenever an I/O access is made to 4 bytes from address
0FFFDh, 0FFFEh, or 0FFFFh. A16# is also asserted when an I/O access is made to 2 bytes from
address 0FFFFh.
A set of I/O accesses (other than ones used for configuration space access) is consumed by the
internal graphics device if it is enabled.
The I/O accesses (other than ones used for configuration space access) are forwarded normally to
the hub interface bus unless they fall within the AGP I/O address range as defined by the
mechanisms explained below. The GMCH will not post I/O Write cycles to IDE. The PCICMD1
register can disable the routing of I/O cycles to the AGP. The GMCH/MCH never responds to I/O
cycles initiated on AGP.
4.4.5.1 AGP/PCI I/O Address Mapping
The GMCH/MCH can be programmed to direct non-memory (I/O) accesses to the AGP bus
interface when CPU initiated I/O cycle addresses are within the AGP I/O address range. This
range is controlled via the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT)
registers in GMCH/MCH Device #1 configuration space.
Address decoding for this range is based on the following concept. The top 4 bits of the respective
I/O Base and I/O Limit registers correspond to address bits A[15:12] of an I/O address. For the
purpose of address decoding, the GMCH/MCH assumes that lower 12 address bits A[11:0] of the
I/O base are zero and that address bits A[11:0] of the I/O limit address are FFFh. This forces the
I/O address range alignment to 4-kB boundary and produces a size granularity of 4 kB.