Datasheet

System Address Map
R
Datasheet 171
range. Note that the High DDR SDRAM space is the same as the Compatible Transaction
Address space. Table 46 describes three unique address ranges:
1. Compatible Transaction Address (Adr C)
2. High Transaction Address (Adr H)
3. TSEG Transaction Address (Adr T)
These abbreviations are used later.
Table 39. SMM Space Transaction Handling
SMM Space Enabled Transaction Address Space (Adr) DRAM Space (DRAM)
Compatible (C) A0000h to BFFFFh A0000h to BFFFFh
High (H) 0FEDA0000h to 0FEDBFFFFh A0000h to BFFFFh
TSEG (T) (TOM-TSEG_SZ) to TOM (TOM-TSEG_SZ) to TOM
4.4.3.3 SMM Access through GART/GTT TLB
CPU accesses through GART/GTT TLB address translation to enabled SMM DDR SDRAM
space are not allowed. Writes will be routed to memory address 0h with byte enables deasserted
and reads will be routed to memory address 0h. If a GART/GTT TLB translated address hits
enabled SMM DDR SDRAM space, the Invalid Graphics Aperture Translation Table Entry Flag
(ITTEF) in the ERRSTS register is set.
AGP and hub interface originated accesses are never allowed to access SMM space directly or
through the GART/GTT TLB address translation. If a GART/GTT TLB translated address hits
enabled SMM SDRAM space, the Invalid Graphics Aperture Translation Table Entry Flag
(ITTEF) in the ERRSTS register is set.
AGP (PIPE/SBA) write accesses through GART/GTT TLB address translation to enabled SMM
DDR SDRAM space will be re-mapped to address 0h with de-asserted byte enables. AGP
(PIPE/SBA) read accesses through GART/GTT TLB address translation to enabled SMM DDR
SDRAM space will be re-mapped to address 0h.
AGP (FRAME) write accesses through GART/GTT TLB address translation to enabled SMM
DDR SDRAM space will be re-mapped to address 0h with de-asserted byte enables. AGP
(PIPE/SBA) read accesses through GART/GTT TLB address translation to enabled SMM DDR
SDRAM space will be re-mapped to address 0h.
All hub interface originated cycles are snooped and subsequently decoded on the FSB. Hub
interface write accesses through GART/GTT TLB address translation to enabled SMM DDR
SDRAM space will be snooped and then remapped to address 0h with de-asserted byte enables.
Hub interface read accesses through GART/GTT TLB address translation to enabled SMM DDR
SDRAM space will be snooped and remapped to address 0h. Any WB resulting from the snoop
will be written to enabled SMM DDR SDRAM.
For CPU, AGP (SBA, PIPE and FRAME), and hub interface originated accesses, if a GART/GTT
TLB translated address hits enabled High SMM transaction space, the access will go to DDR
SDRAM (if 256-MB SDRAM or more) without being re-mapped.