Datasheet

System Address Map
R
Datasheet 167
4.4.2.1 Extended SMRAM Address Range (HSEG and TSEG)
The HSEG and TSEG SMM transaction address spaces reside in this extended system memory
area.
4.4.2.2 HSEG
SMM mode processor accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. Non-
SMM mode processor accesses to enabled HSEG are considered invalid are terminated
immediately on the FSB. The exceptions to this rule are Non-SMM mode Write Back cycles that
are re-mapped to SMM space to maintain cache coherency. AGP and hub interface originated
cycles to enabled SMM space are not allowed. Physical DDR SDRAM behind the HSEG
transaction address is not re-mapped and is not accessible.
4.4.2.3 TSEG
TSEG is 1-MB in size and is at the top of physical system memory. SMM mode processor
accesses to enabled TSEG access the physical DDR SDRAM at the same address. AGP and hub
interface originated cycles to enabled SMM space are handled as invalid cycle type with reads
and writes to location 0 and byte enables turned off for writes. When the extended SMRAM space
is enabled, CPU accesses to the TSEG range without SMM attribute or without WB attribute are
forwarded to the hub interface.
Non-SMM mode CPU accesses to enabled TSEG are considered invalid and are terminated
immediately on the FSB. The exceptions to this rule are Non-SMM-mode Write Back cycles that
are directed to the physical SMM space to maintain cache coherency. Hub interface originated
cycles that enable SMM space are not allowed.
The size of the SMRAM space is determined by the USMM value in the SMRAM register. When
the extended SMRAM space is enabled, non-SMM CPU accesses and all other accesses in this
range are forwarded to the hub interface. When SMM is enabled the amount of system memory
available to the system is equal to the amount of physical DDR SDRAM minus the value in the
TSEG register which is fixed at 1 MB for the Intel 852GME GMCH and Intel 852PM MCH.
4.4.2.4 Dynamic Video Memory Technology (DVMT)
The IGD supports DVMT in a non-graphics system memory configuration. DVMT is a
mechanism that manages system memory and the internal graphics device for optimal graphics
performance. DVMT-enabled software drivers, working with the memory arbiter and the
operating system, utilize the system memory to support 2D graphics and 3D applications. DVMT
dynamically responds to application requirements by allocating the proper amount of display and
texturing memory.
4.4.2.5 PCI Memory Address Range (Top of Main System Memory to 4 GB)
The address range from the top of main DDR SDRAM to 4-GB (top of physical system memory
space supported by the GMCH/MCH) is normally mapped via the hub interface to PCI.
With an internal graphics configuration (Intel 852GME GMCH), there are two exceptions to this
rule.