Datasheet

Datasheet 153

3.11.6 CC – Class Code Register (Device #2)

Address Offset: 09−0Bh

Default Value: 030000h

Access: Read Only

Size: 24 bits

This register contains the device programming interface information related to the Sub-Class code

and Base Class code definition for the IGD. This register also contains the Base Class code and

the function sub-class in relation to the Base Class code.

Bit Description

23:16 Base Class Code (BASEC): 03=Display controller

15:8 Sub-Class Code (SCC):

Function 0: 00h=VGA compatible or 80h=Non VGA

Function 1: 80h=Non VGA

7:0 Programming Interface (PI): 00h=Hardwired as a Display controller.

3.11.7 CLS – Cache Line Size Register (Device #2)

Address Offset: 0Ch

Default Value: 00h

Access: Read only

Size: 8 bits

The IGD does not support this register as a PCI slave.

Bit Description

7:0 Cache Line Size (CLS) – RO

3.11.8 MLT – Master Latency Timer Register (Device #2)

Address Offset: 0Dh

Default Value: 00h

Access: Read Only

Size: 8 bits

The IGD does not support the programmability of the master latency timer because it does not

perform bursts.

Bit Description

7:0 Master Latency Timer Count Value – RO