Datasheet

Register Description
R
Datasheet 151
3.11.3 PCICMD – PCI Command Register (Device #2)
Address Offset: 04−05h
Default: 0000h
Access: Read Only, Read/Write
Size: 16 bits
This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The
PCICMD register in the IGD disables the IGD PCI compliant master accesses to Main System
memory.
Bit Description
15:10 Reserved
9 Fast Back-to-Back (FB2B)⎯RO.
8 SERR# Enable (SERRE) ⎯RO
7 Address/Data Stepping⎯RO
6 Parity Error Enable (PERRE) ⎯RO
5 Video Palette Snooping (VPS) ⎯RO
4 Memory Write and Invalidate Enable (MWIE) ⎯RO
3 Special Cycle Enable (SCE) ⎯RO
2 Bus Master Enable (BME) ⎯R/W: This bit determines if the IGD is to function as a PCI
compliant master.
0= Disable IGD bus mastering (default).
1 = Enable IGD bus mastering.
1 Memory Access Enable (MAE) ⎯R/W: This bit controls the IGD’s response to system
memory space accesses.
0= Disable (default).
1 = Enable.
0 I/O Access Enable (IOAE) ⎯R/W: This bit controls the IGD’s response to I/O Space
accesses.
0 = Disable (default).
1 = Enable.