Datasheet

R
Datasheet 15
supported
• Max 165 MHz dot clock
• Variety of DVO devices supported
• Compliant with DVI Specification 1.0
⎯ Dedicated LFP LVDS interface
• Single or dual channel LVDS panel
support up UXGA panel resolution with
frequency range from 25 MHz to 112
MHz (single channel/dual channel)
• Supports data format of 18-bpp
• Compliant with ANSI/TIA/EIA –644-
1995 specification
• SSC support of 0.5%, 1.0%, and 2.5%
center and down spread with external
SSC clock
• LCD panel power sequencing compliant
with SPWG timing specification
• Integrated PWM interface for LCD
backlight inverter control
• Bi-linear Panel fitting
⎯ Color Specular Lighting
⎯ Z Bias support
⎯ 16 and 24-bit Z Buffering
⎯ 16 and 24-bit W Buffering
⎯ 8-bit Stencil Buffering
⎯ Double and Triple Render Buffer support
⎯ Maximum 3D resolution of 1600x1200 at
85-Hz (contact your Intel Field
Representative for detailed display
information, i.e. pixel depths, etc.)
⎯ Fast Clear support