Datasheet

Register Description
R
148 Datasheet
Bit Description
2 ISA Enable (ISAEN): Modifies the response by the GMCH/MCH to an I/O access issued by the
CPU that target ISA I/O addresses. This applies only to I/O addresses that are enabled by the
IOBASE and IOLIMIT registers. When this bit is set to 1, GMCH/MCH will not forward to
PCI_B/AGP any I/O transactions addressing the last 768 bytes in each 1-KB block even if the
addresses are within the range defined by the IOBASE and IOLIMIT registers. Instead of going
to PCI_B/AGP these cycles will be forwarded to hub interface where they can be subtractively or
positively claimed by the ISA bridge. If this bit is 0 (default) then all addresses defined by the
IOBASE and IOLIMIT for CPU I/O transactions will be mapped to PCI_B/AGP.
1 Reserved
0 Parity Error Response Enable (PEREN): Controls GMCH/MCH’s response to data phase
parity errors on PCI_B/AGP. G_PERR# is not implemented by the GMCH/MCH. However, when
this bit is set to 1, address and data parity errors detected on PCI_B are reported via the HI
SERR messaging mechanism, if further enabled by SERRE1. If this bit is reset to 0, then
address and data parity errors on PCI_B/AGP are not reported via the GMCH/MCH hub
interface SERR messaging mechanism. Other types of error conditions can still be signaled via
SERR messaging independent of this bit’s state.
The bit field definitions for VGAEN and MDAP are detailed in the following table.
VGAEN:
MDAP Description
0 0 All References to MDA and VGA space are routed to hub interface.
0 1 Illegal combination
1 0 All VGA references are routed to this bus. Exclusive MDA references are routed to hub
interface.
1 1 All VGA references are routed to this bus. All MDA references are routed to hub
interface.
3.10.21 ERRCMD1 - Error Command Register (Device #1)
Address Offset: 40h
Default Value: 00h
Access: Read Only, Read/Write
Size: 8 bits
Bit Description
7:1 Reserved
0 SERR on Receiving Target Abort (SERTA): When this bit is 1 the GMCH/MCH
generates an SERR message over hub interface upon receiving a target abort on
PCI_B. When this bit is set to 0, the GMCH/MCH does not assert an SERR message
upon receipt of a target abort on PCI_B. SERR messaging for Device #1 is globally
enabled in the PCICMD1 register.