Datasheet

Register Description
R
Datasheet 147
3.10.20 BCTRL - Bridge Control Register (Device #1)
Address Offset: 3Eh
Default Value: 00h
Access: Read Only, Read/Write
Size: 8 bits
This register provides extensions to the PCICMD1 register that are specific to PCI to PCI bridges.
The BCTRL provides additional control for the secondary interface (i.e. PCI_B/AGP) as well as
some bits that affect the overall behavior of the “virtual” PCI to PCI bridge embedded within
GMCH/MCH, e.g. VGA compatible address ranges mapping.
Bit Description
7:6 Reserved
5 Master Abort Mode (MAMODE): This means when acting as a master on AGP/PCI_B the
GMCH/MCH will drop writes on the floor and return all 1s during reads when a Master Abort
occurs (Set to 1).
4 Reserved
3 VGA Enable (VGAEN): This bit controls the routing of CPU initiated transactions targeting VGA
compatible I/O and memory address ranges. When this bit is set, the GMCH will forward the
following CPU accesses to the AGP:
1) memory accesses in the range 0A0000h to 0BFFFFh
2) I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of
ISA address aliases - A[15:10] are not decoded)
When this bit is set, forwarding of these accesses issued by the CPU is independent of the I/O
address and memory address ranges defined by the previously defined base and limit registers.
Forwarding of these accesses is also independent of the settings of the bit 2 (ISA Enable) of this
register if this bit is “1”.
If the VGA enable bit is set, then accesses to IO address range x3BCh-x3BFh are forwarded to
hub interface.
If the VGA enable bit is not set, then accesses to IO address range x3BCh-x3BFh are treated
just like any other IO accesses, i.e. the cycles are forwarded to AGP if the address is within
IOBASE and IOLIMIT and ISA enable bit is not set, otherwise they are forwarded to hub
interface.
If this bit is “0” (default), then VGA compatible memory and I/O range accesses are not
forwarded to AGP. but rather they are mapped to primary PCI unless they are mapped to AGP
via I/O and memory range registers defined above (IOBASE, IOLIMIT, MBASE, MLIMIT,
PMBASE, PMLIMIT)
The following table shows the behavior for all combinations of MDA and VGA:
VGA
MDA Behavior
0 0 All References to MDA and VGA Go To hub interface (Default)
0 1 Reserved
1 0 All References To VGA Go to AGP. MDA-only references (I/O
Address 3BF and aliases) will go to hub interface.
1 1 VGA References go to AGP; MDA references go to hub interface