Datasheet

146 Datasheet

3.10.19 PMLIMIT1 - Prefetchable Memory Limit Address Reg

(Device #1)

Address Offset: 26h

Default Value: 0000h

Access: Read Only, Read/Write

Size: 16 bits

This register controls the CPU to PCI_B prefetchable memory accesses routing based on the

following formula:

PREFETCHABLE_MEMORY_BASE=< address =<PREFETCHABLE_MEMORY_LIMIT

The upper 12 bits of the register are read/write and correspond to the upper 12 address bits

A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-only and return zeroes

when read. This register must be initialized by the configuration software. For the purpose of

address decode address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined

memory address range will be at the top of a 1MB aligned memory block. Note that prefetchable

memory range is supported to allow segregation by the configuration software between the

memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e.

prefetchable) from the CPU perspective.

Bit Description

15:4 Prefetchable Memory Address Limit (PMLIMIT): Corresponds to A[31:20] of the upper

limit of the address range passed by bridge Device #1 across AGP/PCI_B.

3:0 Reserved