Datasheet

Datasheet 145

3.10.18 PMBASE1 - Prefetchable Memory Base Address Reg

(Device #1)

Address Offset: 24h

Default Value: FFF0h

Access: Read Only, Read/Write

Size: 16 bits

This register controls the CPU to PCI_B prefetchable memory accesses routing based on the

following formula:

PREFETCHABLE_MEMORY_BASE=< address =<PREFETCHABLE_MEMORY_LIMIT

The upper 12 bits of the register are read/write and correspond to the upper 12 address bits

A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-only and return zeroes

when read. This register must be initialized by the configuration software. For the purpose of

address decode address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory

address range will be aligned to a 1-MB boundary.

Bit Description

15:4 Prefetchable Memory Address Base (PMBASE): Corresponds to A[31:20] of the lower

limit of the address range passed by bridge device 1 across AGP/PCI_B.

3:0 Reserved