Datasheet

144 Datasheet

3.10.17 MLIMIT1 - Memory Limit Address Register (Device #1)

Address Offset: 22h

Default Value: 0000h

Access: Read Only, Read/Write

Size: 16 bits

This register controls the CPU to PCI_B non-prefetchable memory access routing based on the

following formula:

MEMORY_BASE=< address =<MEMORY_LIMIT

The upper 12 bits of the register are read/write and correspond to the upper 12 address bits

A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-only and return zeroes

when read. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh.

Thus, the top of the defined memory address range will be at the top of a 1MB aligned memory

block. NOTE: Memory range covered by MBASE and MLIMIT registers are used to map non-

prefetchable PCI_B/AGP address ranges (typically where control/status memory-mapped I/O data

structures of the graphics controller will reside) and PMBASE and PMLIMIT are used to map

prefetchable address ranges (typically graphics local memory). This segregation allows

application of USWC space attribute to be performed in a true plug-and-play manner to the

prefetchable address range for improved CPU-AGP memory access performance.

Bit Description

15:4 Memory Address Limit (MLIMIT): Corresponds to A[31:20] of the memory address that

corresponds to the upper limit of the range of memory accesses that will be passed by

the device 1 bridge to AGP/PCI_B.

3:0 Reserved