Datasheet

142 Datasheet

3.10.15 SSTS1 - Secondary Status Register (Device #1)

Address Offset: 1Eh

Default Value: 02A0h

Access: Read Only, Read/Write Clear

Size: 16 bits

SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with a

secondary side (i.e. PCI_B/AGP side) of the “virtual” PCI to PCI bridge embedded within

GMCH/MCH.

Bit Description

15 Detected Parity Error (DPE): This bit is set to a 1 to indicate GMCH/MCH’s detection of

a parity error in the address or data phase of PCI_B/AGP bus transactions. Software

sets DPE1 to 0 by writing a 1 to this bit.

14 Reserved

13 Received Master Abort Status (RMAS): When the GMCH/MCH terminates a Host to

PCI_B/AGP with an unexpected master abort, this bit is set to 1. Software resets this bit

to 0 by writing a 1 to it.

12 Received Target Abort Status (RTAS): When a GMCH/MCH -initiated transaction on

PCI_B/AGP is terminated with a target abort, RTAS1 is set to 1. Software resets RTAS1

to 0 by writing a 1 to it.

11 Reserved

10:9 DEVSEL# Timing (DEVT): This 2-bit field indicates the timing of the DEVSEL# signal

when the GMCH/MCH responds as a target on PCI_B/AGP, and is hard-wired to the

value 01b (medium) to indicate the time when a valid DEVSEL# can be sampled by the

initiator of the PCI cycle.

8 Reserved

7 Fast Back-to-Back (FB2B): This bit is hardwired to 1, since GMCH/MCH as a target

supports fast back-to-back transactions on PCI_B/AGP.

6 Reserved

5 66/60 MHz capability (CAP66): The AGP/PCI_B bus is capable of 66Mhz operation

(Set to 1)

4:0 Reserved