Datasheet

Register Description
R
140 Datasheet
3.10.11 SUBUSN1 - Subordinate Bus Number (Device #1)
Address Offset: 1Ah
Default Value: 00h
Access: Read/Write
Size: 8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI_B/AGP.
This number is programmed by the PCI configuration software to allow mapping of configuration
cycles to PCI_B/AGP.
Bit Description
7:0 Subordinate Bus Number (BUSN): This register is programmed by configuration
software with the number of the highest subordinate bus that lies behind the Device #1
bridge. When only a single PCI device resides on the AGP/PCI_B segment, this register
will contain the same value as the SBUSN1 register.
3.10.12 SMLT1 - Secondary Bus Master Latency Timer (Device #1)
Address Offset: 1Bh
Default Value: 00h
Access: Read Only, Read/Write
Size: 8 bits
This register controls the bus tenure of the GMCH/MCH on AGP/PCI the same way Device#0
MLT controls the access to the PCI_A bus.
Bit Description
7:3
Secondary MLT Counter Value (MLT): Programmable, default = 0 (SMLT
disabled)
2:0
Reserved