Datasheet

Register Description
R
138 Datasheet
3.10.6 SUBC1 - Sub-Class Code (Device #1)
Address Offset: 0Ah
Default Value: 04h
Access: Read Only
Size: 8 bits
This register contains the Sub-Class Code for the GMCH/MCH Device #1. This code is 04h
indicating a PCI-to-PCI bridge device.
Bit Description
7:0 Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Bridge
into which the Device #1 of the GMCH/MCH falls. The code is 04h indicating a PCI to
PCI bridge.
3.10.7 BCC1 - Base Class Code (Device #1)
Address Offset: 0Bh
Default Value: 06h
Access: Read Only
Size: 8 bits
This register contains the Base Class Code of the GMCH/MCH Device #1. This code is 06h
indicating a Bridge device.
Bit Description
7:0 Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code
for the GMCH device #1. This code has the value 06h, indicating a Bridge device.
3.10.8 HDR1 - Header Type (Device #1)
Address Offset: 0Eh
Default Value: 01h
Access: Read Only
Size: 8 bits
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit Description
7:0 Header Type Register (HDR): This read only field always returns 01 to indicate that
GMCH/MCH Device #1 is a single function device with bridge header layout. Writes to
this location have no effect.