Datasheet

Register Description
R
Datasheet 137
3.10.4 PCISTS1 - PCI Status Register (Device #1)
Address Offset: 06h
Default Value: 00A0h
Access: Read Only, Read/Write Clear
Size: 16 bits
PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with
the primary side of the “virtual” PCI to PCI bridge embedded within the GMCH/MCH.
Bit Description
15 Reserved
14 Signaled System Error (SSE): This bit is set to 1 when GMCH/MCH Device#1
generates an SERR message over hub interface for any enabled Device #1 error
condition. Device #1 error conditions are enabled in the ERRCMD, PCICMD1 and
BCTRL registers. Device #1 error flags are read/reset from the ERRSTS and SSTS1
register. Software clears this bit by writing a 1 to it.
13:8 Reserved
7 Fast Back-to-Back (FB2B): Indicates that the AGP/PCI_B interface always supports
fast back to back writes (set to 1).
6 Reserved
5 66/60 MHz capability (CAP66): Since the AGP/PCI bus is 66 MHz capable (set to 1).
4:0 Reserved
3.10.5 RID - Revision Identification (Device #1)
Address Offset: 08h
Default Value: 02h
Access: Read Only
Size: 8 bits
This register contains the revision number of the GMCH device #1. These bits are read only and
writes to this register have no effect.
Bit Description
7:0 Revision Identification Number: This is an 8-bit value that indicates the revision
identification number for the GMCH/MCH.
Intel 852GME = 02
Intel 852PM = 02