Datasheet

136 Datasheet

3.10.3 PCICMD1 - PCI Command Register (Device #1)

Address Offset: 04h

Default Value: 0000h

Access: Read Only, Read/Write

Size: 16 bits

Bit Description

15:9 Reserved

8 SERR Message Enable (SERRE): This bit is a global enable bit for Device #1 SERR

messaging. The GMCH/MCH communicates the SERR# condition by sending an SERR

message to the ICH4-M. If this bit is set to a 1, the GMCH/MCH is enabled to generate

SERR messages over hub interface for specific Device 1 error conditions that are

individually enabled in the BCTRL1 register. The error status is reported in the PCISTS1

GMCH/MCH for Device #1.

7 Address/Data Stepping (ADSTEP): Address/data stepping is not implemented in the

GMCH/MCH, and this bit is hardwired to 0. Writes to this bit position have no effect.

6:5 Reserved

4 Memory Write and Invalidate Enable (MWIE): This bit is implemented as Read Only

and returns a value of 0 when read.

3 Special Cycle Enable (SCE): This bit is implemented as Read Only and returns a value

of 0 when read.

2 Bus Master Enable (BME): When the Bus Master Enabled is set to “0” (default), AGP

Master initiated Frame# cycles will be ignored by the GMCH/MCH. The result is a

master abort. Ignoring incoming cycles on the secondary side of the PCI to PCI bridge

effectively disabled the bus master on the primary side.

When 1, AGP master initiated Frame# cycles will be accepted by the GMCH/MCH if they

hit a valid address decode range. This bit has no affect on AGP Master originated SBA

or PIPE# cycles.

1 Memory Access Enable (MAE): This bit must be set to 1 to enable the Memory and

Pre-fetchable memory address ranges defined in the MBASE1, MLIMIT1, PMBASE1,

and PMLIMIT1 registers. When set to 0 all of Device #1’s memory space is disabled.

0 IO Access Enable (IOAE): This bit must be set to1 to enable the I/O address range

defined in the IOBASE1, and IOLIMIT1 registers. When set to 0 all of Device #1’s I/O

space is disabled.