Datasheet

Register Description
R
134 Datasheet
3.10 PCI to AGP Configuration Registers (Device #1,
Function #0)
Table 35. Device 1 is the Virtual PCI to AGP Bridge (Device #1, Function #0))
Register Name
Register
Symbol
Register
Start
Register
End
Default Value Access
Vendor
Identification
VID 00 01 8086h RO
Device
Identification
DID 02 03 3581h RO
PCI Command
Register
PCICMD1 04 05 0000h RO, R/W
PCI Status
Register
PCISTS1 06 07 00A0h RO, R/WC
Revision
Identification
RID 08 08 01h
02h
RO
Sub-Class Code SUBC1 0A 0A 04h RO
Base Class Code BCC1 0B 0B 06h RO
Header Type HDR1 0E 0E 01h RO
Primary Bus
Number
PBUSN1 18 18 00h RO
Secondary Bus
Number
SBUSN1 19 19 00h R/W
Subordinate Bus
Number
SUBUSN1 1A 1A 00h R/W
Secondary Bus
Master Latency
Timer
SMLT1 1B 1B 00h RO,R/W
I/O Base Address
Register
IOBASE1 1C 1C F0h RO,R/W
I/O Limit Address
Register
IOLIMIT1 1D 1D 00h RO,R/W
Secondary Status
Register
SSTS1 1E 1F 02A0h RO,R/WC
Memory Base
Address Register
MBASE1 20 21 FFF0h RO,R/W
Memory Limit
Address Register
MLIMIT1 22 23 0000h RO,R/W
Prefetchable
Memory Base Limit
Address Reg.
PMBASE1 24 25 FFF0h RO,R/W
Prefetchable
Memory Limit
Address Reg.
PMLIMIT1 26 27 0000h RO,R/W